In a memory bus, the impedances of a memory device and a memory controller can be trained against each other. The training may enable the memory bus to detect a data eye of a signal, such as a signal communicated over a link coupling the memory device to the memory controller. The data eye may include a point on the signal that (when located and sampled) may be used to identify an associated bit as being either a logical one or a zero. Training may include adjusting an operating parameter of the memory controller or the memory device. An illustrative operating parameter may include a voltage level associated with the signal.
Mismatching impedances of the memory device and the memory controller may reduce a width of the data eye, or timing margin, and compromise data accuracy.